Summary of MIPS Assembly Language instructions

Notation:

mnemonic
instruction
syntax
action
A.  Load and store instructions
lw
load word
lw $reg, addr
$reg <-- M[addr]
sw
store word
sw $reg, addr
M[addr] <-- $reg
lb
load byte
lb $reg, addr
[$reg]7-0 <-- m[addr]
[$reg]31-8 <-- m[addr]7
lbu
load byte unsigned
lbu $reg, addr
[$reg]7-0 <-- m[addr]
[$reg]31-8 <-- 0
sb
store byte
sb $reg, addr
m[addr] <-- [$reg]7-0
li
load immediate
li $reg, const
$reg <-- const
la
load address
la $reg, addr
$reg <-- addr
B.  Data movement instructions
move
move
move $dest, $src
$dest <-- $src
C.  Arithmetic and logical instructions
add
add
add $dest, $src1, $src2
$dest <-- $src1 + $src2
sub
subtract
sub $dest, $src1, $src2
$dest <-- $src1 - $src2
mul
multiply
mul $dest, $src1, $src2
$dest <-- $src1 * $src2
div
divide
div $dest, $src1, $src2
$dest <-- $src1 / $src2
rem
remainder
rem $dest, $src1, $src2
$dest <-- $src1 mod $src2
and
bitwise and
and $dest, $src1, $src2
$dest <-- $src1 & $src2
or
bitwise or
or $dest, $src1, $src2 $dest <-- $src1 | $src2
xor
bitwise exclusive or
xor $dest, $src1, $src2 $dest <-- $src1 ^ $src2
nor
bitwise nor
nor $dest, $src1, $src2 $dest <-- ~ ($src1 | $src2)
not
bitwise not
not $dest, $src1 $dest <-- ~ $src1
D.  Branch instructions
b
branch
b addr
$pc <-- addr
beq
branch if equal
beq $r1, $r2, addr
if $r1 == $r2 then $pc <-- addr
bgt
branch if greater than
bgt $r1,$r2, addr
if $r1 > $r2 then $pc <-- addr
bge
branch if greater than or equal
bge $r1, $r2, addr
if $r1 >= $r2 then $pc <-- addr
blt
branch if less than
blt $r1, $r2, addr
if $r1 < $r2 then $pc <-- addr
ble
branch if less than or equal
ble $r1, $r2, addr
if $r1 <= $r2 then $pc <-- addr
bne
branch if not equal
bne $r1, $r2, addr
if $r1 != $r2 then $pc <-- addr
bltz
branch if negative
bltz $r1, addr
if $r1 < 0 then $pc <-- addr
blez
branch if not positive
blez $r1, addr
if $r1 <= 0 then $pc <-- addr
bgtz
branch if positive
bgtz $r1, addr
if $r1 > 0 then $pc <-- addr
bgez
branch if not negative
bgez $r1, addr
if $r1 >= 0 then $pc <-- addr
E.  Shift instructions
sll
shift left logical
sll $dest, $src, nbits
$dest <-- $src << nbits
srl
shift right logical
srl $dest $src, nbits
$dest <-- $src >> nbits
sra
shift right arithmetic
sra $dest, $src, nbits
$dest <-- ($src >> nbits) with
 sign extended
F.  Jump instructions
j
jump
j addr
$pc <-- addr
jr
jump register
jr $reg
$pc <-- $reg
jal
jump and link
jal addr
$31 <-- $pc+4; $pc <-- addr
G.  Set instructions
slt
set less than
slt $dest, $src1, $src2
if $src1<$src2 then $dest=1 else $dest=0
slti
set less than immediate
slti $dest, $src1, imm
if $src1<imm then $dest=1 else $dest=0
sle
set less or equal
sle $dest, $src1, $src2 if $src1<=$src2 then $dest=1 else $dest=0
sgt
set greater than
sgt $dest, $src1, $src2 if $src1>$src2 then $dest=1 else $dest=0
sge
set greater or equal
sge $dest, $src1, $src2 if $src1>=$src2 then $dest=1 else $dest=0
seq
set on equal
seq $dest, $src1, $src2 if $src1==$src2 then $dest=1 else $dest=0
sne
set on not equal
sne $dest, $src1, $src2 if $src1!=$src2 then $dest=1 else $dest=0