Final Exam Review
Final office hours:
Friday, December 16: 10am-noon
Monday, December 19: 1-3 pm
Comprehensive part:
- Quantitative analysis
- Amdahl's law
- performance equation: time = IC x CPI / clock rate
- ISA design
- Classification
- Addressing
- CISC vs RISC
- Intel
- Pipelining (Appendix A)
- Basics
- data path
- pipeline registers
- computing speedup
- Hazards
- structural hazards
- data hazards (RAW, WAW, WAR) and forwarding
- control hazards
- branch penalty
- delayed branch
- Exceptions
- Multicycle operations and floating point
- ILP
- Dependencies
- Data dependencies
- Name dependencies
- output dependency
- antidependency
- Dynamic scheduling
Since the midterm exam:
Expect about 67 to 75% of the exam to cover material since the midterm.
- Instruction Level Parallelism
- Branch prediction
- Multiple issue
- Speculation
- Loop unrolling
- VLIW
- Software pipelining
- Memory Organization
- Cache memory
- Direct, set associative, and fully associative mapping
- Performance enhancement
- reducing hit time
- reducing miss rate
- reducing miss penalty
- Main memory
- Virtual memory
- Direct-mapped page and segment tables
- Translation lookaside buffer
- Multiprocessing and multithreading
- Multiprocessor design
- Symmetric multiprocessing (UMA)
- Distributed shared memory multiprocessing (NUMA)
- Cache coherence
- On-chip multiprocessing and multithreading