DLSim FSM / Multiplier

Author: Richard Salter

This is an 8-bit shift multiplier using a control unit that loads and executes a finite state machine (FSM) description. Current FSM state and transitions are shown.
Reset ON, Reset OFF
  1. Using the spinners on the Multiplicand and Mulitplier Inputs, select hexidecimal numbers to multiply; note that Clear ON, Clear OFF resets these signal generators to 0.
  2. Click Start ON; this is required to transition from the "Start" control state.
  3. Start clock, or manually clock by repeating > ON, > OFF
  4. Product will appear in the Running Sum register when Control State is "done". The "done" state transitions back to "Start", and multiplication will repeat unless Start OFF is clicked before the "Start" state returns.
Circuit is locked; unlock using Tools | Unlock Circuit
adder8, adder4, adder
The 8-bit carry-ripple adder is built over 2 levels (4-bit and 1-bit). The 1-bit adder is implemented using a FPGA-type logic lookup table.

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last modified April 5, 2009 by rms@cs.oberlin.edu